1. Field of the Invention
This invention relates to bistable non-volatile semiconductor latches, and, more particularly, to a flip-flop circuit which includes electrically erasable, electrically programmable memory elements for setting and storing the configuration of programmable semiconductor circuitry.
2. Description of the Related Art
There is a strong need to remember the state of conditions entered or derived in semiconductor devices whenever the devices are on. These states must reliably configure the devices to act in one way or another. Examples of devices needing different configurations with the same basic device are EPLD's (Electrically Programmable Logic Devices), FPGA's (Field Programmable Gate Arrays) and memory devices that require repairing defective rows or columns of memory cells with spare or redundant rows or columns of memory cells.
Since these devices and systems have no prior knowledge of the desired conditions, non-volatile memory would be needed to store the state of conditions when the devices are turned off. When the devices are turned back on, the state of conditions are restored for proper device operation.
An array of non-volatile memory cells is a way of storing the desired conditions, but because the structure of an array of memory cells requires additional circuitry to function, simultaneous access of all states in the array is not practical. Sometimes in the EPLD case, an array of non-volatile memory cells on or off chip is used, and during device and system power up, the entire content of the array is downloaded into state latches on the device which store and configure the device while it is on. The problem with this scheme is off chip it requires more system board space and algorithms for downloading the data, and on chip it requires a memory array with its associated overhead circuitry. Both methods require algorithms for downloading the data into state latches on chip.
For memory devices, the above scheme does not work since on power up, the memory device needs to start working right away without downloading from a non-volatile memory. Usually, memory devices incorporate fuse links to configure redundant elements and are an efficient way to implement redundancy on a memory device, but this method requires large development and production cost.
A better approach would be integrate a non-volatile latch into the configuration logic of these circuits; however, almost all manufacturable non-volatile memory elements available today require voltages during the erase and write operations that greatly exceed the typical operating voltage range of logic circuitry. In order to accommodate these higher voltages, special high voltage devices and structures must be fabricated in an integrated fashion with the standard logic devices. The additional manufacturing steps required to integrate the high voltage devices adds non-productive manufacturing costs to the logic and increases logic production yield losses. Oftentimes, these two factors increase the cost of the logic well beyond what customers would be willing to accept.
It is therefore desirable to integrate non-volatile memory elements in a novel manner that would eliminate the need for voltages significantly higher that the typical operation voltage range of the logic circuitry.
Therefore, what is needed is a method and apparatus for providing instantaneous logic configuration upon power up when data latch devices are used to configure the state of the logic without incorporating large numbers of extra devices and manufacturing steps.